Peregrine UltraCMOS™ Digital Step Attenuators Feature Serial Addressability

Newest 5- and 6-bit DSAs offer exceptional broadband linearity

San Diego, California, June 9, 2009 — Peregrine Semiconductor Corporation, a leading supplier of high-performance RF CMOS and mixed-signal communications ICs, today released the latest in the new UltraCMOS™ Digital Step Attenuator (DSA) 50Ω series. Building on their high-performance predecessors, along with direct and latched parallel interface logic these new HaRP™-enhanced devices also offer highly flexible serial programmability with attenuation options covering a 7.75 dB (PE43501)and 15.75 dB (PE43601) attenuation range in 0.25 dB steps.

The PE43501 and PE43601 DSAs offer best-in-class linearity, outstanding attenuation accuracy and low Insertion Loss (IL). As with all UltraCMOS silicon-on-sapphire RFICs, there is no gate lag nor phase drift providing exceptionally fast settling time, making them ideal for next generation wireless protocols such as LTE, WiMAX and TD-SCDMA (China’s 3G standard for mobile telecommunication).  These devices provide the industries best linearity and broadband accurracy for cellular base stations, repeaters and femtocells.

These new 50-Ohm DSAs have an operating frequency range of near DC up to 6 GHz with exceptional low- frequency performance, Input IP3 > +60 dBm at 3GHz, superior noise immunity and ESD tolerance of 500V HBM. The device operates with equivalent performance at 3.3V and 5V supply with very low power consumption, allowing the use of a single device in both the RF and IF radio sections to save board space.

Peregrine’s newest DSAs provide many additional features, including on-board CMOS logic which facilitates 2.75 V control, and a high-α state at power-up (PUP). The devices are available in the compact, RoHS-compliant QFN 32- lead package (5x5x0.85 mm). All products are sampling now and are priced at PE43501: $2.12 (50K units); and PE43601: $2.28 (50K units).

About UltraCMOS™ Technology and the HaRP Technology Innovation

UltraCMOS™ mixed-signal process technology is a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate providing with high yields and competitive costs. This technology delivers significant performance advantages over competing processes such as GaAs, SiGe BiCMOS and bulk silicon CMOS in applications where RF performance, low power and high levels of integration are paramount. The Company’s revolutionary HaRP™ technology further exploits the fundamental benefits of silicon-on-sapphire, enabling dramatic improvements in harmonic results, linearity and overall RF performance which today remain unmatched by any other RF process technology.

About Peregrine Semiconductor

Peregrine Semiconductor Corporation designs, manufactures, and markets high-performance communications RF ICs for the wireless infrastructure and mobile wireless; broadband CATV/DTV; communications infrastructure; and high-rel markets. Manufactured on the Company’s proprietary UltraCMOS™ mixed-signal process technology, Peregrine products are uniquely poised to meet the needs of a global RF design community in high-growth applications such as WCDMA, EDGE and GSM digital cellular and mobile TV; broadband communications such as DTV/PCTV/DVR; and in high-reliability applications such as telecom infrastructure, industrial, automotive, military and satellite systems. Peregrine UltraCMOS devices are manufactured under licensed foundry partnerships with world-class CMOS semiconductor manufacturers located in Japan, Taiwan, Korea and Australia. The Company, headquartered in San Diego, California, maintains global sales support operations and a worldwide technical distribution network. Additional information is available on the web at www.psemi.com.

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The Peregrine Semiconductor name and logo are registered trademarks and UltraCMOS, HaRP and DuNE are trademarks of Peregrine Semiconductor Corporation. All other trademarks are the property of their respective owners.

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    Industry-leading linearity and RF performance
    HaRP™ technology enhancement reduces gate lag and insertion loss drift
    Monolithic CMOS solution that integrates RF, analog and digital
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    HaRP™ technology enhancement reduces gate lag and insertion loss drift
    Monolithic CMOS solution that integrates RF, analog and digital
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    HaRP™ technology enhancement reduces gate lag and insertion loss drift
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    Monolithic CMOS solution that integrates RF, analog and digital
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    HaRP™ technology enhancement reduces gate lag and insertion loss drift
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    Excellent ESD protection and reliability
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